1. Field of the Invention
The present invention relates generally to nonvolatile memory integrated circuits, and more particularly, to proper loading of data during power-up.
2. Description of Related Art
Electrically programmable and erasable nonvolatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a nonvolatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A flash memory is a type of electronic memory media in which the memory cells can be rewritten and the contents in the memory cells are kept stored without power. A typical flash memory has a life span of about 100 k to 300 k write cycles. In a dynamic random access memory or a static random access memory, a single byte is erased as opposed to a flash memory where one or more multi-bit blocks are erased and written. A flash memory combines the features of EPROM density with the electrical erase ability in an EEPROM.
Conventional flash memory cells are designed with flashing-gate transistors where each floating-gate transistor has a source region, a drain region, a floating-gate layer and a control-gate layer. An access operation is carried out by applying a bias signal to each of the regions in the flash-gate transistor. A write operation is generally carried out by a channel hot-carrier injection such that there is a flow of electrons between the source region and the drain region that are accelerated toward a floating gate in response to a positive bias applied to a control gate. A common type of erase operation uses Fowler-Nordheim tunneling, which electrically floats the drain region while applying a high negative voltage. A read operation generally includes the step of sensing a current between the source region and the drain region, i.e., the MOSFET current in response to a bias being applied to the control gate. If a memory cell has been programmed, the threshold voltage will be near or above the control gate bias in which the resulting current is low to non-existent. If the memory cell is erased, the threshold voltage is kept well below the control gate bias so that the current is substantially higher.
An electrical voltage generated from a power supply during power-up can fluctuate in which the voltage may be unstable. Configuration information of a system is typically loaded into registers during power-up for setting the configuration of the system. However, with the voltage fluctuating during power-up, it potentially could cause an error in reading on whether the configuration information has been properly loaded into the registers.
One conventional solution for verifying that the configurable information has been properly read from the nonvolatile memory is to supply the memory cells with a high voltage. The high voltage is a value that is greater than a supply voltage, particularly for a lower-power device in the 1.65 volts range. A circuit that generates a voltage greater than a supply voltage like a charge pump is likely to cause a large and unstable power variation during power-up.
Another conventional solution uses a 3 volts device to establish a bandgap reference for detecting whether a read voltage is ready. A precondition requires that the bandgap reference is established during a power-on reset. However, the configuration information could be loaded incorrectly when there are interferences to the voltage during power-up. There is also the difficulty to apply this solution to a low voltage product. For example, in a 1.8 volts product, a low bound of the power-on reset may be set to 1 volt, which presents the difficulty to design a bandgap reference at this voltage level.
Accordingly, there is a need to provide a circuit and method for an accurate read of configurable information during power-up for nonvolatile memories including low voltage flash memories.